VPX554
Xilinx Virtex UltraScale+ XCVU47P, CPU NXP LX2160A with Dual FMC+, 6U VPX
Description:
VPX554 is a 6U VPX board utilizing Xilinx Virtex UltraScale+ XCVU47P FPGA with CPU from NXP LX2160A.
The VPX554 has dual FMC+ sites per VITA57.4 which route all the LA/HA/HB as well as all the FMC+ 32 SERDES (DP) to the FPGA.
The FPGA XCVU47P has integrated 16GB of High Bandwidth Memory (HBM) which can provide large memory buffer space. In addition, the FPGA has 16GB of DDR4 memory. The FPGA has 12x SERDES routed to the P6 location via VITA 66.5 optical. These SERDES could utilize the hardcore CMAC of the XCVU47P to run at 100GbE or as 40GbE/10GbE, Aurora, etc. The FPGA has 12 additional RX/TX SERDES routed to P3 which could operate up to 28Gbaud per lane. Ports 0-3 of the P3 connector are routed to the FPGA PCIe Hardcore. The FPGA routes to P4/P5 16x LVDS (which could be configured as single ended lanes vs. differential per pair) as well as additional singled ended 48x GPIO which could be configured in banks of x8 as +3.3V or +5V.
The CPU is based on the NXP LX2160A which has 16 A72 cores running at 2.2GHz each.
The health management CPU, the LX2160A CPU and the FPGA RS-232 are routed to a USB-to-RS-232 interface which is accessed through USB 2.0.
VPX554 has a PLL clock jitter cleaner and can provide clocks to both of the FMCs, the FPGA, and/or the protocol clocks for P0/P4 connectors.
The health management is based on the VITA 46.11 with Tier 2 support.
The unit is available in a range of temperature and shock/vibe specifications per ANSI/VITA 47, up to V3 and OS2.
Please contact us for details of Conduction Cooled versions.
Key Features:
- Xilinx Virtex UltraScale+ XCVU47P FPGA with 16GB of High Bandwidth Memory (HBM)
- Processor Layerscape LX2160A (16-core, ARM Cortex A72 Core) @ 2.2GHz per core
- Dual FMC+ per VITA 57.4
- From FPGA dual 100G/40G/10G speed to the rear via VITA66.5 optical (P6 Location)
- CPU with 32GB of DDR4 with ECC
- 8GB of eMMC
- 1TB of NVMe
- Dual USB 3.0/2.0 with dual RS-422/485 (to P2)
- 12x RX/TX SERDES from FPGA to P3
- Additional 16GB of DDR-4 to FPGA
- Differential and/or single I/O to P4/P5
- Clock PLL jitter cleaner
- Health Management through dedicated processor