VPX574
Dual RF Agile Transceiver with Front I/O, 3U VPX
Description:
VPX574 provides dual integrated RF transceivers, each based on AD9364 in conjunction with AM3060 built in amplifiers. Track and cable lengths between front panel RF connectors and AD9364 are tightly matched. The module is compatible with Analog Devices RadioVerse design tools.
The module features a shared clock between the ADC’s, DAC’s and SERDES (VPX REF_CLK).
The module has 8 TX/RX SERDES, PCI 3.0 x4 (PL), Dual GbE, to the P1 connector and LVDS and M‑LVDS GPIO to the P2 connector, with CPU RS‑232 to front panel.
P0 connector features M-LVDS signal pairs AUX_CLK+/- and REF_CLK+/-.
The FPGA has interface to a single DDR4 memory channel (64-bit wide). This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host.
VPX574 is based on Xilinx UltraScale+ XCZU15EG MPSoC FPGA, which has 3528 DSP Slices and 746k logic cells. The XCZU15EG includes quad-core ARM application processor, dual-core ARM real-time processor and Mali graphics processing unit, as well as over 26 Mb of block RAM and 31 Mb of UltraRAM.
The module has onboard 64 GB of Flash, 128 MB of Boot Flash and an SD Card as an option.
Key Features:
- Dual RF transceiver (AD9364)
- Xilinx UltraScale+ XCZU15EG FPGA
- 8 GB of 64-bit wide DDR4 Memory (single bank) with ECC
- MPSoC with block RAM and UltraRAM
- Health Management through dedicated Processor